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DS4266
DDR Clock Oscillator
_______________________________________________________________________________________
3
ELECTRICAL CHARACTERISTICS (continued)
(VCC = 3.135V to 3.465V, TA = -40°C to +85°C, unless otherwise noted.)
PARAMETER
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
LVDS
Output High Voltage
VOHLVDSO
100
differential load (Note 1)
1.475
V
Output Low Voltage
VOLLVDSO
100
differential load (Note 1)
0.925
V
Differential Output Voltage
|VODLVDSO|
100
differential load
250
425
mV
Output Common-Mode Voltage
Variation
VLVDSOCOM
100
differential load
150
mV
Change in Differential Magnitude
or Complementary Inputs
|VODLVDSO|
100
differential load
25
mV
Offset Output Voltage
VOFFLVDSO
100
differential load (Note 1)
1.125
1.275
V
Differential Output Impedance
ROLVDSO
80
140
LVSSLVDSO
OUTN or OUTP shorted to ground and
measure the current in the shorting path
40
Output Current
LLVDSO
OUTN or OUTP shorted together
6.5
mA
Output Rise Time (Differential)
tRLVDSO
20% to 80%
175
ps
Output Fall Time (Differential)
tFLVDSO
80% to 20%
175
ps
Duty Cycle
DCYCLE_LVDS
48
52
%
Propagation Delay from OE Going
Low to Logical 1 at OUTP
tPA1
200
ns
Propagation Delay from OE Going
High to Output Active
tP1A
200
ns
LVPECL
Output High Voltage
VOH
Output connected to 50
at PECL_BIAS
at VCC - 2.0V
VCC -
1.085
VCC -
0.88
V
Output Low Voltage
VOL
Output connected to 50
at PECL_BIAS
at VCC - 2.0V
VCC -
1.825
VCC -
1.62
V
Differential Voltage
VDIFF_PECL
Output connected to 50
at PECL_BIAS
at VCC - 2.0V
0.595
0.710
V
Rise Time
tR-PECL
200
ps
Fall Time
tF-PECL
200
ps
Duty Cycle
DCYCLE_PECL
48
52
%
Propagation Delay from OE Going
Low to Output High Impedance
tPAZ
200
ns
Propagation Delay from OE Going
High to Output Active
tPZA
200
ns
Note 1: All voltages referenced to ground.
Note 2: AC parameters are guaranteed by design and not production tested.
Note 3: Frequency stability is calculated as:
ΔfTOTAL = ΔfTEMP + ΔfVCC x (3.3 x 5%) + ΔfLOAD + ΔfAGING.
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